- Work as Engineer in System LSI Design and Verification: responsible for designing and verifying complex integrated circuits and systems, ensuring their functionality, reliability, and performance.
- Develop and implement architectural specifications for large-scale integrated circuits, utilizing the latest design methodologies and tools.
- Plan and execute comprehensive verification strategies, including simulation, formal verification. Write and debug test benches, test cases, and test sequences to validate the functionality of the integrated circuits. Conduct functional and performance testing of LSI designs, identifying and resolving bugs and discrepancies.
- To commit process compliance in the assigned task.
- To ensure the TSDV security rules and protect the copyright of Corporation.
Digital Design & Verification Engineer [ Ba Đình - HN ]
![Calendar](https://assets-iconicjob-vn.imgix.net/images/iconicjob/common/calendar.png)
![Code Job](https://assets-iconicjob-vn.imgix.net/images/iconicjob/common/code-job.png)
Tóm tắt công việc
![Salary](https://assets-iconicjob-vn.imgix.net/images/iconicjob/common/salary.png)
![Place](https://assets-iconicjob-vn.imgix.net/images/iconicjob/common/place.png)
- Hà Nội
![Level](https://assets-iconicjob-vn.imgix.net/images/iconicjob/common/level.png)
![Briefcase](https://assets-iconicjob-vn.imgix.net/images/iconicjob/common/briefcase.png)
Mô tả công việc
Yêu cầu công việc
- Bachelor or higher degree in Electronics - Telecommunication Engineering, Electrical Engineering, Computer Engineering, or related fields.
- From 2 years’ working experience in LSI development.
- Proven experience in LSI design and verification, working with RTL design, functional verification, and verification methodologies.
- Proficiency in hardware description languages (HDLs) such as Verilog/ System Verilog/ VHDL.
- Familiarity with industry-standard EDA tools for LSI design and verification, such as Cadence(NCSim), Synopsys (VCS/DVE/Verdi), or Mentor Graphics.
- Knowledge of scripting languages (e.g., Python, Perl, Shell scripting) for automation and validation tasks.
- Have basic working experience on Linux environment.
- English: Equivalent to TOEIC 600.
* Preferred Skills:
- Having experience in performing constraint random verification (using UVM/OVM) or formal verification (property checking using VCF, Jasper Gold) is a plus.
- Able to work under high pressure.
* Benefit:
- Being a member of a giant corporation, you will receive following benefit:
- Salary: NEGOTIATION. Full Social, Medical & Unemployment Insurance.
- Bonus once a year. Incentive twice a year. Total package up to 15 months salary/ year.
- Review performance twice a year.
- Work in well - equipped and professional IT environment and IT community.
- To be trained and/or instructed by Japanese Specialists in Vietnam as well as in Japan and others.
- Become member of a giant corporation.
- Many opportunities to work or study in Japan.