Design & Verification Engineer - Công Ty Công Nghệ Của Nhật Bản

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- Input the specifications required by the customer, and specific design verification work is performed and OUTPUT is performed using the following languages.
- Functional specifications (English)
- Implementation specifications (English)
- RTL (Verilog)
- Verification Strategy Book (English)
- Verification item table (English)
- Verification environment construction (SystemVerilog / SVA / UVM / C / C ++)
- Verification scenario (SystemVerilog / SVA / UVM / C / C ++)
- Verification environment manual (English)
- Verification result report (English)

- More than 3 years working experience of semiconductor field
- Have technology and knowledge : Design skill priority, Verilog, SystemVerilog, SVA, UVM Methodology, C, SystemC, and so on
- Intermediate level English skill

* Phúc lợi:
- Duty allowance
- IT Admin allowance
- Lunch allowance
- Commute allowance 
- Child allowance
- Project Leader allowance
- Long-term service allowance (5 years or more)
- Business trip allowance
- Company trip
- Language allowance
- Insurance support
- Uniform (once a year)